MPSoC-MSI
MPSoC-MSI
Master Slave Interface for MPSoC-WB
0.00€
A Master Slave Interface (MSI) is a model of communication where one device has unidirectional control over other devices. A master is selected from a group of eligible devices, with the other devices acting in the role of slaves. The ARM Advanced Microcontroller Bus Architecture (AMBA) and Wishbone Bus are an open-standard, on-chip interconnect specification for the connection and management of functional blocks.
Work: Implementation in VHDL & (System)Verilog of a Master Slave Interface and simulation in GHDL & Icarus Verilog.
Cores Inside QueenField Devices
Open ISA RISC-V
Open ISA OpenRISC
