DevOps

QueenField

Paco Reina Campo

1 PLAN

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DevOps Toolchain

Hardware Project Workflow

Hardware Project Workflow

Software Project Workflow

Software Project Workflow

Hardware DevOps
CONTROL	DEVELOP	OPERATION
certification	bench	sim
doc	model	compilation
quality	validation	synthesis
requirements	rtl/src
	source
	verification

FOLDER	NORMATIVE	TECHNOLOGY
requirements	IEEE STD 1850-2010	PSL
	OMG-2.5.1.	UML
certification	RTCA DO-254
	RTCA DO-178C
quality	ISO 9001-2015
doc	IEEE STD 1685-2014	IP-XACT
	IEEE STD 1735-2014
source	RTCA DO-254
	RTCA DO-178C
bench	IEEE STD 1076-2019	VHDL
	IEEE STD 1800-2017	SystemVerilog
model	IEEE STD 1076-2019	VHDL
	IEEE STD 1800-2017	SystemVerilog
validation	IEEE STD 1076-2019	OSVVM
rtl/src	IEEE STD 1076-2019	VHDL
	IEEE STD 1364-2005	Verilog
verification	IEEE STD 1800.2-2020	UVM

1.1 REQUIREMENTS

1.2 QUALITY ASSURANCE

1.3 CERTIFICATION

1.4 DESIGN LIFECYCLE DATA

2 CODE

GIT

Save credentials

git config --global credential.helper cache
git pull

Recursively clone repository “REPOSITORY” of user “USER”

git clone --recursive https://github.com/USER/REPOSITORY.git

Remove submodule “repository”

git rm -rf repository

Add submodule “repository” with the content of the repository “REPOSITORY” of the user “USER”

git submodule add --force https://github.com/USER/REPOSITORY.git repository

Save work “WORK”

git add *
git commit -m "WORK"
git push origin master

Remove last commit

git reset --hard HEAD^
git push origin -f

Update repository “FORKED-REPOSITORY” of the user “USER”

git remote add upstream https://github.com/USER/FORKED-REPOSITORY.git
git fetch upstream
git checkout master
git rebase upstream/master
git push -f origin master

SVN

Save credentials

svn checkout --username USER --password PASSWORD https://github.com/USER/REPOSITORY

Remove submodule “repository”

svn delete repository

Save work “WORK”

git add *
svn commit -m "WORK"

2.1 SOURCE

2.2 MODEL

2.2.1 Hardware

find . -type f -name '*.vhd' -exec emacs -batch {} -f vhdl-beautify-buffer -f save-buffer \;

find . -type f -name '*.sv' -exec verible-verilog-format \
--inplace \
--wrap_spaces=2 \
--column_limit=256 \
--port_declarations_alignment=align \
--port_declarations_indentation=indent \
--named_port_alignment=align \
--named_port_indentation=indent \
--formal_parameters_alignment=align \
--named_parameter_alignment=align \
--class_member_variable_alignment=align \
--enum_assignment_statement_alignment=align \
--struct_union_members_alignment=align \
--assignment_statement_alignment=align \
--case_items_alignment=align \
--distribution_items_alignment=align \
--module_net_variable_alignment=align \
--nocompact_indexing_and_selections \
--expand_coverpoints {} \;

find . -type f -name '*.vhd' -exec vhdl2verilog {} \;

find . -type f -name '*.sv' -exec verilog2vhdl {} \;

2.2.2 Software

2.3 DESIGN

2.3.1 Hardware: RTL

2.3.2 Software: SRC

3 BUILD

3.1 SIM

3.1.1 VHDL

3.1.1.1 GHDL

3.1.2 Verilog

3.1.2.1 Icarus Verilog

3.2 COMPILATION

3.2.1 MSP430 GNU Compiler Collection

3.2.1.1 MSP430 GNU C

3.2.1.2 MSP430 GNU C++

3.2.1.3 MSP430 GNU Go

3.2.1.4 MSP430 GNU Rust

3.2.2 OpenRISC GNU Compiler Collection

3.2.2.1 OpenRISC GNU C

3.2.2.2 OpenRISC GNU C++

3.2.2.3 OpenRISC GNU Go

3.2.2.4 OpenRISC GNU Rust

3.2.3 RISC-V GNU Compiler Collection

3.2.3.1 RISC-V GNU C

3.2.3.2 RISC-V GNU C++

3.2.3.3 RISC-V GNU Go

3.2.3.4 RISC-V GNU Rust

3.3 SYNTHESIS

3.3.1 ASIC for Design

3.3.1.1 Yosys-Qflow

type:

cd synthesis/qflow
source flow.sh

3.3.2 FPGA for Model

3.3.2.1 Yosys-Symbiflow