ELECTRONIC ENGINEER
System Level (Hierarchical Description) The System Level abstraction of a system only looks at its biggest building blocks like processing units or peripheral devices. At this level the circuit is
September 10, 2021
Why Choose QueenField
Mixed Implementations
Digital designs implemented in VHDL and SystemVerilog.
UVM and Formal Verification
Digital designs simulated and verified using universal and formal methods.
100% Open Hardware
Open Source Hardware Descriptions and Open Source Tools used.
Products
Hardware Systems
Software Systems
Intelligence Systems
Financial Systems
More than 5 year experience in Hardware and Software Systems
Integrated Circuits (ASIC & FPGA) described in VHDL & Verilog; verified and synthesized with open source tools; and printed with open standard cells.
Printed Circuits Boards drawn, printed, verified and tested with open source tools.
New
MPSoC-OR1K
Multi-Processor System on Chip with OR1K
SoC-MSP430
System on Chip with MSP430
PU-RISCV
Processing Unit with RISCV
QueenField
Modeling, Describing, Simulating (System Level, RTL, Switch Level), Verifying (System Level, RTL, Switch Level), Synthesizing, Optimizing, Planning, Placing, Timing, Routing, Checking and Printing Electronic Circuits.
Procedural
Building open source hardware devices based on mixed implementations (VHDL & SystemVerilog) using open source tools.
Academic
Building hardware devices based on the Scientific Method, seeking to minimize the influence of subjectivity at work, reinforcing the validity of the results.
Universal
Building hardware devices with formal verification and traditional simulation including the standard features only.
Building hardware devices with formal verification and traditional simulation including the standard features only.
Blog
FRONT END HARDWARE ENGINEER
Behavioral Level (Structural Description) entity At the Behavioural Level abstraction a language aimed at hardware description such as Verilog or VHDL is used to describe the circuit, but so-called behavioural
September 10, 2021
BACK END HARDWARE ENGINEER
Logical Gate Level At the Logical Gate Level the design is represented by a netlist that uses only cells from a small number of single-bit cells, such as basic logic
September 10, 2021
Cores Inside QueenField Devices
Open ISA RISC-V
Open ISA OpenRISC
